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E2E1020-27-Y3 Semiconductor
Semiconductor MSM65354/65353A
GENERAL DESCRIPTION
This MSM65354/65353A version: Jan. 1998 Previous version: Nov. 1996
8-Bit Microcontroller with A/D Converter (with LCD Driver)
The MSM65354/MSM65353A is a high performance 8-bit microcontroller that employs OKI original CPU core nX-8/50. The MSM65354 contains 24K-byte program memory, 640byte data memory, LCD driver, A/D converter and shift register. The MSM65353A contains 16K-byte program memory, 384-byte data memory, LCD driver, A/D converter and shift register. Also available is the MSM65P354, which replace the on-chip program memory with one-time PROM.
FEATURES
* Operating range Operating voltage Operating temperature Operating frequency (dual clock) High speed side Low speed side Current consumption (Typ.) High speed side : : : : : 2.7V to 5.5V -20C to +70C 0 to 10MHz (@VDD=5V10%) 0 to 5MHz (@VDD=2.7V to 5.5V) 32.768kHz (@VDD=2.7V to 5.5V) 5mA (@5MHz, VDD=3V) 20mA (@10MHz, VDD=5V) 1.5mA (@5MHz, VDD=3V, Halt mode) 4mA (VDD=3V), Stop mode) 45mA (@32.768kHz, VDD=3V) 400ns (@10MHz), 800ns (@5MHz) 8-bit CPU core nX-8/50 24K-byte program memory + 256-byte data memory (MSM65354) 16K-byte program memory (MSM65353A) 384-byte data memory + SFR 32 4 (selectable duty cycle from 1/4, 1/3 or 1/2 with software) 5 ports 8 bits 1 port 1 bit, 1 port 8 bits 1 port 1 bit 8-bit auto-reload timer 3 (one of them can be used for the shift clock of shift register) Watch timer counter 1 Time base counter 1 (14 bits) 1 line, selectable from 1000Hz to 16000Hz (@10MHz) 2ch, with 16-byte automatic transfer function 1, clock sync mode 1 8ch, 8 bits (4ch of them can start the CPU according to level detection interrupt) 1/20
Low speed side * Minimum instruction execution time * CPU core * General memory space
: : : :
* Local memory space * LCD driver * I/O port Input-output port Input port Output port * Timer
: :
: : : : : : : : :
* Counter * Buzzer output circuit * Shift register * A/D converter
Semiconductor * External interrupt * Remote control circuit : :
MSM65354/65353A Three lines, selectable from rising edge/ falling edge/both edges Receives signal in 32.768kHz/5MHz/ 10MHz operations 13
* Interrupt source : * Package: 100-pin plastic QFP (QFP100-P-1420-0.65-BK4) (Product name:MSM65354-GS-BK4, MSM65353A-GS-BK4) indicates the code number. * Others : CPU clock can be an OSC, half-OSC, XT or 4 times XT clock : Time base counter clock can be selected with 1/4n of a CPU clock (n=1 to 8) : Stop status can be set at each port (high impedance or prior status is retained) : Pull-up or open can be set for each inputoutput port
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Semiconductor
BLOCK DIAGRAM
XT XT OCS0 OSC1 RESET CLKOUT* XSTOP*
RAM (256 bytes) OSC. CONT. CPU CORE INST. DEC. T/C ALU IR TBC GMAR PC
BUS CONT.
ROM (24K bytes)
RAM (384 bytes)
WDT
BUZZER OUTPUT
BZ*
VDD GND
8-bit TIMER 3 AR BR PSW SP LMAR
8-bit SHIFT REG. (16-BYTE AUTOMATIC TRANSFER FUNCTION)
T1OUT* T0CK* GATE* SFTO0* SFTI0* SFTCK0* SFTO1* SFTI1* SFTCK1* INT0* INT1* INT2* INT3*
8-bit SHIFT REG.
8-bit A/D C 8ch I/O PORT LCD DRIVER WATCH TIMER
INTERRUPT CONT.
MSM65354/65353A
AGND
AI0-7*
AVDD VRH
SEG31
COM4 SEG0
VDD3 VDD2 VDD1 VDDL COM1
P0
P1
P2
P3
*secondary function of each port **The MSM65353A contains 16K byte ROM only
P4
P5
P6
REMOTE CONT.
RMCIN*
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Semiconductor
PIN CONFIGURATION (TOP VIEW)
94 RESET 93 P2.0/SFTCK0
,
92 P2.1/SFTI0 91 P2.2/SFTO0 97 VDDL 96 P6.1 (OUT) 90 P2.3/INT2 95 P6.0 (IN) 100 VDD3 99 VDD2 98 VDD1 89 P2.4
MSM65354/65353A
82 OSC0
81 OSC1
83 GND
88 P2.5
87 P2.6
86 P2.7
85 XT
84 XT
COM1 COM2 COM3 COM4 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
44 45 46 47 48 49 50
P0.0/INT0 P0.1/HSTOP P0.2/T1OUT P0.3/T1OUT P0.4/INT1/GATE P0.5/CLKOUT P0.6 P0.7/BZ VDD P1.0 P1.1 P1.2 P1.3 P1.4/RMCIN P1.5/SFTCK1 P1.6/SFTI1 P1.7/SFTO1 P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.7 P5.0 P5.1 P5.2 P5.3 P5.4
31
32 33
34 35 36
37
38
39 40
41
42
SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 AGND P3.0/AI0/INT3 P3.1/AI1/INT3 P3.2/AI2/INT3 P3.3/AI3/INT3 P3.4/AI4 P3.5/AI5 P3.6/AI6 P3.7/AI7 VRH AVDD P5.7 P5.6 P5.5
100-Pin Plastic QFP
43
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MSM65354/65353A
PIN DESCRIPTIONS Basic Function
Function Pin 72 83 47 Power Supply 37 98 99 100 97 82 Symbol VDD GND AVDD AGND VDD1 VDD2 VDD3 VDDL OSC0 Type -- -- -- -- -- -- -- -- I Digital ground Analog supply voltage (5V) Analog ground Bias supply pin for LCD driver Bias supply pin for LCD driver Bias supply pin for LCD driver Bias control pin for LCD driver Oscillation input pin on the OSC side: Connect to a quartz oscillator (ceramic resonator), or input external clock. Oscillation output pin on the OSC side: Oscillation 81 OSC1 O Connect to a quartz oscillator (ceramic resonator). When external clock is input to the OSC0 pin, the OSC1 pin should be open. 84 85 XT XT I O Oscillation input pin on the XT side: Connect to a quartz oscillator of 32.768kHz. Oscillation output pin on the XT side: Connect to a quartz oscillator of 32.768kHz. Description Digital supply voltage (5V)
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MSM65354/65353A
Basic Function (Continued)
Function Pin Symbol Type Description System reset input: When this pin is set to the "L" level, the internal Control 94 RESET I status is initialized to start execution of instructions from address 0040H. The input is pulled up to VDD with an internal pull-up resistor. 8-bit input-output port (port 0): 80 to 73 P0.0 to P0.7 I/O Each of bits 0 to 7 is configured to be input or output by use of the direction register of port 0 (P0DIR). In addition to the basic function as the input-output port, a secondary function is allocated to each of P0.0 through P0.7. See Secondary function. 8-bit input-output port (port 1): 71 Ports to 64 P1.0 to P1.7 I/O Each of bits 0 to 7 is configured to be input or output by use of the direction register of port 1 (P1DIR). In addition to the basic function as the input-output port, a secondary function is allocated to each of P1.0 through P1.7. See Secondary function. 8-bit input-output port (port 2): 93 to 86 P2.0 to P2.7 I/O Each of bits 0 to 7 is configured to be input or output by use of the direction register of port 2 (P2DIR). In addition to the basic function as the input-output port, a secondary function is allocated to each of P2.0 through P2.3. See Secondary function.
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Basic Function (Continued)
Function Pin 38 to 45 63 to 56 55 Ports to 48 95 Symbol P3.0 to P3.7 P4.0 to P4.7 P5.0 to P5.7 P6.0 (IN) I I/O I/O I Type Description 8-bit input port (port 3): Each of P3.0 to P3.7 funcitons as analog input channel of A/D converter. 8-bit input-output port (port 4): 8-bit input-output port. 8-bit input-output port (port 5): Each of bits 0 to 7 is configured to be input or output by the direction register of port 5 (P5DIR). 1-bit input port (port 6.0): 1-bit input port. 1-bit output port (port 6.1): P6.1 96 (OUT) COM1 to COM4 SEG0 to SEG31 O LCD segment signal output pins. O LCD common signal output pins. O Pulled high at the time of reset. If this pin is set to the "0" level during reset, this IC goes into a test mode, disabling execution of the user program. 1 to LCD Driver 4 5 to 36
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Secondary Function
Function Pin Symbol Type Description Secondary function of P0.0: 80 INT0 I Input pin for external interrupt 0. This pin can receive input at the rising edge, falling edge, or both the rising/falling edges. Secondary function of P0.4: Input pin for external interrupt 1. This pin can 76 External Interrupt INT1 I receive input at the rising edge, falling edge, or both the rising/falling edges. Also used as a gate signal input pin to enable or disable the count of timer 0. Secondary function of P2.3: 90 INT2 I Input pin for external interrupt 2. This pin can receive input at the rising edge, falling edge, or the both rising/falling edges. 38 to 41 INT3 I Secondary function of P3.0 to 3.3: Input pin for external interrupt 3. This pin can receive input at the rising edge, falling edge, or both the rising/falling edges. Secondary function of P0.1: Hardware stop mode input pin. When this pin is Control 79 HSTOP I set to the "L" level while the HSTP bit in SBYCON is set to "1", the hardware stop mode is entered. In the hardware stop mode, oscillation on the OSC side is stopped for low power consumption. Timer 0 77 T0CK I Secondary function of P0.3: External clock input pin for timer 0. Secondary function of P0.2: Timer 1 78 38 A/D Converter to 45 T1OUT AI0 to AI7 I O Output pin that provides waveform with a cycle twice the overflow of timer 1. Secondary function of P3.0 to 3.7: These are used for analog input channels in A/D conversion.
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MSM65354/65353A
Secondary Function (Continued)
Function Clock Output Pin 75 Symbol CLKOUT Type O Description Secondary function of P0.5: Output pin for OSCCLK divided by 2 or 4 or for XTCLK divided by 2 or 4. Buzzer Output Remote Control Input 73 67 91 92 BZ RMCIN SFTO0 SFTI0 O I O I Secondary function of P0.7: Output pin for buzzer. Secondary function of P1.4: Input pin for remote control. Secondary function of P2.2: Data output pin for shift register 0. Secondary function of P2.1: Data Input pin for shift register 0. Secondary function of P2.2: Sync. clock input-output pin for shift register 0. 93 Shift Register 64 65 SFTO1 SFTI1 O I SFTCK0 I/O This provides a clock output when used as the master, or it functions as clock input when used as a slave. Secondary function of P1.7: Data output pin for shift register 1. Secondary function of P1.6: Data Input pin for shift register 1. Secondary function of P1.5: Sync. clock input-output pin for shift register 1. 66 SFTCK1 I/O This provides a clock output when used as the master, or it functions as clock input when used as a slave.
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MSM65354/65353A
MEMORY MAPS
General Memory Space 0FFFFH Data Memory Local Memory Space 1FFH Unused space Data Memory Page 1 6000H* 100H SFR 80H R Data Memory 40H 30H 20H 10H 0 Page 0
Local Register Set 3 Local Register Set 2 Local Register Set 1 Local Register Set 0
0FF00H
Program Memory 100H Vector Call Table 80H Program Memory 40H 20H 0
Interrupt Vector Table Vector Call Table
Internal Memory
*
4000H, in the case of MSM65353A
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MSM65354/65353A
ABSOLUTE MAXIMUM RATINGS
Parameter Supply Voltage Input Voltage Output Voltage Maximum Allowable Dissipation Storage Temperature Symbol VDD VI VO PD TSTG Ta = 25C, per package Ta = 25C, per output -- Ta = 25C Condition Rating -0.3 to 7.0 -0.3 to VDD+0.3 -0.3 to VDD+0.3 400 50 -55 to +150 mW C V Unit
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage Memory Hold Voltage Oscillation Frequency*1
External Clock Operating Frequency*2
Symbol VDD VDDMH fOSC fXT fEXTCLK Top
Condition -- fOSC = 0Hz -- VDD = 2.7 to 5.5 -- --
Range 2.7 to 5.5 2.0 to 5.5 1 to 10 32.768/75 1 to 10
-20
Unit V MHz kHz MHz C
Operating Temperature
to +70
*1 Determined by the crystal oscillator or ceramic resonator to be used. *2 External clock cannot be used in the XT pin.
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MSM65354/65353A
ELECTRICAL CHARACTERISTICS
DC Characteristics 1 (VDD=4.5 to 5.5V)
Parameter "H" Input Voltage 1 "H" Input Voltage 2 "L" Input Voltage "H" Output Voltage 1 "H" Output Voltage 2 "L" Output Voltage 1 "L" Output Voltage 2
*3 *4 *3 *4 *1 *2
(GND = 0V, Ta = -20 to +70C) Min. 2.4 0.75VDD
--
Symbol
Condition CPUCLK=1MHz CPUCLK=1MHz CPUCLK=1MHz IOH = -200mA IOH = -400mA IOL = 1.6mA IOL = 3.2mA I = +10mA VDD1 = 1.4V, I = 10mA VDD2 = 2.8V, I = 10mA VDD3 = 4.2V, I = -10mA VI = VDD/0V VI = 0V, VDD = 5V f = 1MHz, Ta = 25C
Stop mode, during LCD stop, no load Stop mode, during LCD operation, no load
*7 *7 *8 *9
Typ. -- -- -- -- -- -- -- -- -- -- -- --
-200
Max. -- -- 0.8 -- -- 0.4 0.4 0.4 VDD1+0.4 VDD2+0.4 -- 10
-400
Unit
VIH1 VIH2 VIL VOH1 VOH2 VOL1 VOL2 V0 V1 V2 V3 ILI2 IIL CI IDD1 IDD2 IDD3 IDD4 IDD5 IDD6
0.75VDD 0.75VDD -- -- -- VDD1-0.4 VDD2-0.4 VDD3-0.4 --
-40
V
Segment and Common Driver Output Voltage
*5 *6
Input Leakage Current
"L" Input Current Input Capacitance Operating Current Consumption VDD = 5V XT = 32kHz OSC = 10MHz
mA pF mA mA mA mA mA mA
-- -- -- -- -- -- --
5 7 15 30 80 8 20
-- 14 30 60 160 16 50
CPUCLK = 32kHz, HALT mode CPUCLK = 32kHz, no load CPUCLK = 10MHz, HALT mode CPUCLK = 10MHz, no load
*1 *2 *3 *4 *5 *6 *7 *8 *9
Excluding OSC0 and RESET Only for OSC0 and RESET Excluding P4 Only for P4 Excluding RESET Only for RESET Including hardware stop mode Measured when OSC clock is stopped but LCD is operated without load Measured when OSC clock is stopped
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MSM65354/65353A
DC Characteristics 2 (2.7V VDD < 4.5V)
Parameter "H" Input Voltage 1 "H" Input Voltage 2 "L" Input Voltage "H" Output Voltage 1 "H" Output Voltage 2 "L" Output Voltage 1 "L" Output Voltage 2
*3 *4 *3 *4 *1 *2
(GND = 0V, Ta = -20 to +70C) Min.
0.3VDD +0.9 0.6VDD +0.6 --
*10
Symbol
Condition CPUCLK=1MHz CPUCLK=1MHz CPUCLK=1MHz IOH = -10mA IOH = -20mA IOL = 10mA IOL = 20mA I = +10mA VDD1 = 1.4V, I = 10mA VDD2 = 2.8V, I = 10mA VDD3 = 4.2V, I = -10mA VI = VDD/0V VI = 0V, VDD = 3V f = 1MHz, Ta = 25C
Stop mode, during LCD stop, no load Stop mode, during LCD operation, no load
*7 *7 *8 *9
Typ. -- -- -- -- -- -- -- -- -- -- -- --
-125
Max. -- --
0.3VDD -0.1
*11
Unit
VIH1 VIH2 VIL VOH1 VOH2 VOL1 VOL2 V0 V1 V2 V3 ILI2 IIL CI IDD1 IDD2 IDD3 IDD4 IDD5 IDD6
0.75VDD 0.75VDD -- -- -- VDD1-0.4 VDD2-0.4 VDD3-0.4 --
-40
-- -- 0.1 0.1 0.4 VDD1+0.4 VDD2+0.4 -- 10
-250
V
Segment and Common Driver Output Voltage
*5 *6
Input Leakage Current
"L" Input Current Input Capacitance Operating Current Consumption VDD = 3V XT = 32kHz OSC = 5MHz
mA pF mA mA mA mA mA mA
-- -- -- -- -- -- --
5 4 8 15 45 1.5 5
-- 8 16 30 90 3 16
CPUCLK = 32kHz, HALT mode CPUCLK = 32kHz, no load CPUCLK = 5MHz, HALT mode CPUCLK = 5MHz, no load
*1 Excluding OSC0 and RESET *2 Only for OSC0 and RESET *3 Excluding P4 *4 Only for P4 *5 Excluding RESET *6 Only for RESET *7 Including hardware stop mode *8 Measured when OSC clock is stopped but LCD is operated without load *9 Measured when OSC clock is stopped *10 More than 3.375V *11 Less than 0.8V
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MSM65354/65353A
AC Characteristics * CPU control
(VDD = 2.7 to 5.5V, GND = 0V, Ta = -20 to +70C) Parameter RESET Pulse Width Symbol tRESW Condition -- Min. 20 Max. -- Unit ns
* Peripheral control 1
Parameter OSC Clock Cycle Clock "L" Pulse Width External Interrupt EXI Pulse Width External Clock Pulse T0 Width GATE Pulse Width Symbol tC tCLW tEXIW tT0CW tT0GW -- Condition VDD = 4.5 to 5.5V 2.7V VDD < 4.5V --
(VDD = 2.7 to 5.5V, GND = 0V, Ta = -20 to +70C) Min. 100 200 0.45tC 4CPUCLK 4CPUCLK 4 tT0CLK
*1
Max. -- -- 0.55tC -- -- --
Unit
ns
*1
*2
*1 CPUCLK : Supply clock to the CPU selected by SBYCON. *2 tT0CLK : Cycle time of timer 0 count clock selected by T0CON.
* Peripheral control 2
Parameter OSC Clock Cycle
SFTCK Cycle
(VDD = 2.7 to 5.5V, GND = 0V, Ta = -20 to +70C) Symbol tC tSFC0, 1 Condition VDD = 4.5 to 5.5V 2.7V VDD < 4.5V MIN 100 200 8CPUCLK *1 4CPUCLK -20 *1 4CPUCLK CL = 100 pF -20 *1
tSFCLW0, 1 -100 tSFCHW0, 1 -100
MAX -- -- -- -- -- -- -- -- --
Unit
SFTCK "L" Pulse Width tSFCLW0, 1 SFTCK "H" Pulse Width tSFCHW0, 1
SFT0, 1 SFTO Setup Time
ns
tSFOS0, 1 tSFOH0, 1 tSFIS0, 1 tSFIH0, 1
SFTO Hold Time SFTI Setup Time SFTI Hold Time
100 100
*1 CPUCLK : Supply clock to the CPU selected by SBYCON. See Timing Diagram.
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A/D Converter Characteristics 1
(VDD = AVDD = VRH = 4.5 to 5.5V, GND = AGND = 0V, Ta = -20 to +70C) Parameter Resolution Linearity Error Differential Linearity Error Zero Scale Error Full Scale Error Crosstalk Conversion Time* Symbol n EL ED EZS EFS ECT tCONV Refer to measuring circuit. fOSC = 10MHz Refer to recommended circuit. Analog input source impedance RI 5kW -- -- -- -- -- -- -- -- -- 16 Condition Min. -- -- Typ. 8 -- Max. -- +1.5 -1.5 0.5 +1.5 -1.5 0.5 -- Unit bit LSB LSB LSB LSB LSB ms/CH
*
The conversion time immediately after GO bit is set to "1" is 14.8ms/CH.
A/D Converter Characteristics 2
(VDD = AVDD = VRH, 2.7V VDD < 4.5V, GND = AGND = 0V, Ta = -20 to +70C) Parameter Resolution Linearity Error Differential Linearity Error Zero Scale Error Full Scale Error Crosstalk Conversion Time* Symbol n EL ED EZS EFS ECT tCONV Refer to measuring circuit. fOSC = 5MHz Refer to recommended circuit. Analog input source impedance RI 5kW -- -- -- -- -- -- -- -- -- 32 Condition Min. -- -- Typ. 8 -- Max. -- +2 -2 1 +2 -2 1 -- Unit bit LSB LSB LSB LSB LSB ms/CH
*
The conversion time immediately after GO bit is set to "1" is 29.6ms/CH.
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MSM65354/65353A
Definition of Terms Resolution Recognizable minimum input analog value. This can be resolved into 28 = 256, that is VRH / 256 Deviation between ideal conversion characteristics as an 8-bit A/D converter and actual conversion characteristics. (Not including quantization error.) Ideal conversion characteristics means a step which divides voltage between VRH and AGND into 256. Shows the smoothness of conversion characteristics. 1LSB = VRH / 256 is ideal for analog input voltage width corresponding to change per 1 bit of digital output. The differential linearity error is the deviation between this ideal bit size and a bit size at arbitrary point in conversion range. Deviation between ideal conversion characteristics of transfer point for digital outputs "000H" to "001H" and actual conversion characteristics. Deviation between ideal conversion characteristics of transfer point for digital outputs "0FEH" to "0FFH" and actual conversion characteristics.
Linearity Error
Differential Linearity Error
Zero Scale Error
Full Scale Error
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Semiconductor * Recommended circuit
MSM65354/65353A
AVDD VRH VDD VDD
MSM65354 /MSM65353A - + AGND Analog Voltage Input 0.1 F RI AI0-7 GND
+ 0.1 47 F F 0V
RI (Analog input source impedance) 5kW
* Crosstalk measuring circuit
- +
5kW
AI0 AI1
Analog Voltage Input 0.1 F
to
Crosstalk is defined as the difference of A/D conversion result between supplying the same voltage to AI0 to AI7 and supplying voltage shown in this left diagram.
AI7
VREF or AGND
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MSM65354/65353A
Timing Diagram
* CPU control
1) RESET Pulse width tRESW RESET
* Peripheral control 1
tC OSC0 tCLW 1) EXI Pulse width INT0 - 2
tEXIW
2) T0 T0CK
tT0CW
tT0GW GATE
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MSM65354/65353A
* Peripheral control 2
1) SFT0, 1 tSFCLW SFTCK
tSFC tSFCHW
tSFOS SFTO tSFIS SFTI
tSFOH
tSFIH
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PACKAGE DIMENSIONS
(Unit : mm)
QFP100-P-1420-0.65-BK4
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 1.54 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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